- Intel webpages on its AVX and AVX-512 instruction sets
- Wikipedia pages on Skylake and Kaby Lake processors
- AnandTech article on Haswell's 128MB embedded DRAM
- AnandTech article on Xeon E5 v4 chips
- Intel webpages on its Xeon Phi chips, and latest "Knights Landing" processor
- Wikipedia page on Xeon Phi chips
- new NERSC Cray supercomputer using Xeon Phis
- future Aurora supercomputer at Argonne
- ExtremeTech article on Xeon Phi Knights Landing workstation
- AnandTech article on Intel's new Xeon D chip with integrated 10GigE networking
- Supermicro's 3U MicroBlade with Xeon D modules providing 28 single-processor nodes
Personal opinion (Mike Giles)
Intel is clearly the dominant vendor in the industry and so everything they do is of interest.
Application developers need to be aware of the importance of vectorisation on the mainstream Xeon chips. As the vector length increases steadily (with plans already to go to 512-bits) developers will be throwing away a lot of the chip's performance if their codes do not vectorise.
Currently, I think the Xeon Phi product (both hardware and software) is immature, but the next generation 'Knights Landing' product may be more interesting. The integration of stacked memory and networking is definitely an important trend for the future.
The Xeon D article was added because it represents an interesting alternative future for HPC, with large systems built of huge numbers of very small SoC (system-on-chip) chips. At present this does not look very likely, but it's definitely possible, and worth keeping an eye on. The success of chips like this will also be very important as Intel fights the challenge from ARM in the area of low power chips.